verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fancytimer”---The complete timer

1、题目This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (counter, sequence recognizer FSM, FSM delay, and combined FSM).We want to create a timer with one input that:is started when a particular input pattern (1101) is detected,shifts in 4 more bits to determine the duration to delay,waits for the counters to finish counting, andnotifies the user and waits for the user to acknowledge the timer.The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. Ill refer to this as the delay[3:0].After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] 1) * 1000 clock cycles. e.g., delay0 means count 1000 cycles, and delay5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isnt counting, the count[3:0] output is dont-care (whatever value is convenient for you to implement).At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).The circuit should reset into a state where it begins searching for the input sequence 1101.Here is an example of the expected inputs and outputs. The x states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4b0001. The last few cycles starts another count with delay[3:0] 4b1110, which will count for 15000 cycles豆包翻译这是五道配套练习题的最后一题整套习题依靠多个小型电路搭建出一个复杂计数器。建议你先完成前面四道前置习题4 位移位递减计数器、序列识别有限状态机、定时控制 FSM、整合型主控 FSM。我们要设计一款单路输入的定时器完整工作流程如下检测到特定比特序列1101后定时器启动继续串行移入后续 4 个比特用来确定定时延时的时长等待计数器完成指定时长的计数向使用者发出计时完成通知并等待使用者的应答确认。串行比特数据流由引脚data输入一旦捕获到1101序列电路需要以最高位优先MSB 先行串行读取接下来的 4 个比特这 4 位比特定义为delay[3:0]决定定时器的延时总时长。读取完毕后状态机拉高counting输出代表电路进入计数阶段。电路需要精确计数 \(\boldsymbol{(delay[3:0]1)\times1000}\) 个时钟周期。 举例delay 0总计数 1000 个时钟周期delay 5总计数 6000 个时钟周期。同时需要对外输出当前剩余时长count[3:0]时序规则前 1000 个周期剩余时长 delay接下来 1000 个周期剩余时长 delay-1以此类推最后 1000 个周期剩余时长 0 电路不在计数阶段时count[3:0]输出值无要求可任意取值以代码实现简便为准。计数全部结束后电路拉高done信号告知用户定时器超时随后持续等待输入ack变为高电平收到应答后电路复位重新开始搜寻起始序列1101。电路复位后将进入初始状态该状态持续搜寻输入序列1101。下文附有输入输出时序示例。波形中标注的x为无关态含义为该时钟周期内状态机无需关注对应输入信号。 举例说明一旦读取完1101序列与 4 位延时参数delay[3:0]在整轮流程结束、重新回到序列搜寻阶段前电路不再读取data输入。 图例示例说明 本次电路读取到delay0001因此总计数 2000 个时钟周期波形末尾启动了新一轮计时delay1110对应总计时长 15000 个时钟周期。2、分析 这道题实在不会开始设置了五种状态但是失败了后面在网上看到成功的解题然后结合豆包分析的3、代码module top_module ( input clk, input reset, // Synchronous reset 同步高电平复位 input data, // 串行输入数据用于匹配1101序列采集延时系数 output [3:0] count,// 输出当前剩余倒计时分段次数等于delay output counting, // 倒计时阶段拉高标志TIMER_SET、TIMER_RUN有效 output done, // 全部计时完成标志等待ack复位 input ack ); // 应答信号ack1时系统回到初始空闲态 //状态定义串行序列1→11→110→1101递进命名 parameter S_IDLE 4b0000; // 空闲初始态等待输入第一个比特1 parameter S_BIT_1 4b0001; // 已匹配序列第1位1 parameter S_BIT_11 4b0010; // 已连续匹配前2位11 parameter S_BIT_110 4b0011; // 已连续匹配前3位110 parameter S_BIT_1101 4b0100; // 完整匹配4位序列1101进入延时系数采集阶段 parameter S_TIMER_SET 4b0101; // 倒计时初始化阶段配置单段1000周期计数器初值 parameter S_TIMER_RUN 4b0110; // 循环倒计时运行每1000个时钟周期count(delay)自减1 parameter S_DONE_WAIT 4b0111; // 计时全部结束拉高done等待ack信号复位回空闲态 reg [3:0] curr_state; // 当前状态寄存器 reg [3:0] next_state; // 下一状态寄存器 reg [11:0] counter; // 全局计数器复用做1101收尾计时 1000周期分段计时 reg [3:0] delay; // 延时系数4bit决定总周期(delay1)*1000直接输出到count //时序逻辑1状态寄存器更新 always(posedge clk) begin if(reset)begin curr_state S_IDLE; // 复位强制回到空闲态 end else begin curr_state next_state; // 时钟沿更新当前状态为预计算的下一状态 end end //组合逻辑状态跳转判断纯组合无锁存 always(*) begin case(curr_state) // 空闲态data1进入第一位匹配否则保持空闲 S_IDLE: next_state data ? S_BIT_1 : S_IDLE; // 已匹配1再来1则匹配11出现0直接重置回空闲 S_BIT_1: next_state data ? S_BIT_11 : S_IDLE; // 已匹配11持续1保持状态出现0进入110状态 S_BIT_11: next_state data ? S_BIT_11 : S_BIT_110; // 已匹配110出现1则完整匹配1101出现0重置回空闲 S_BIT_110: next_state data ? S_BIT_1101 : S_IDLE; // 1101匹配成功计数器递减至0时采集结束进入计时初始化 S_BIT_1101: next_state (counter 12d0) ? S_TIMER_SET : S_BIT_1101; // 计时初始化固定跳转至倒计时运行态 S_TIMER_SET: next_state S_TIMER_RUN; // 倒计时运行计数器归零delay为0全部计时结束进入等待ack态 S_TIMER_RUN: next_state (counter 12d0 delay 4b0) ? S_DONE_WAIT : S_TIMER_RUN; // 结束等待ack有效则复位到空闲否则保持等待 S_DONE_WAIT: next_state ack ? S_IDLE : S_DONE_WAIT; default: next_state S_IDLE; // 异常状态兜底复位 endcase end //时序逻辑2计数器、延时系数delay赋值更新 always(posedge clk) begin if(reset) begin counter 12d0; // 复位计数器清零 delay 4b0; // 复位延时系数清零 end else begin case(curr_state) // 刚进入110状态给计数器赋值3用于后续4拍采集倒计时 S_BIT_110: begin counter 12d3; end // 1101采集阶段计数器逐拍递减移位寄存连续4bit输入作为delay S_BIT_1101: begin counter counter - 12d1; delay {delay[2:0],data}; end // 计时初始化counter999单段计数区间0~999刚好1000个时钟周期 S_TIMER_SET: begin counter 12d999 - 12d1; end // 倒计时循环每满1000周期delay-1否则计数器正常自减 S_TIMER_RUN: begin if(counter 12d0) begin counter 12d999; delay delay - 4d1; end else begin counter counter - 12d1; end end default: ; // 空闲、比特匹配、结束等待阶段计数器与delay无改动 endcase end end //输出端口连线定义 assign count delay; assign counting (curr_state S_TIMER_SET | curr_state S_TIMER_RUN); assign done (curr_state S_DONE_WAIT); endmodule